A serial memory is a memory that is accessed by a bit stream over a bus having a small number of wires, typically two, one for data and one for a clock or synchronizing signal. Oftentimes, it is advantageous to be able to fine tune the serial memory. Typically, non-volatile bits are used to accomplish fine tuning of a serial memory. In the past, such non-volatile bits were stored by fuses and became known as “fuse bits”. Today these bits are frequently retained in non-volatile memory cells. Use of fuse bits provides an easy and efficient way to make adjustments to a serial memory.
Fuse bits are configuration data for ancillary semiconductor memory support circuits particularly for serial memories, allowing control or change of configuration of the ancillary circuits for read or write operations. For example, fuse bits can specify reference voltages for sense amplifiers or voltages for charge pumps or pulse duration for controlling charge pump switches. In the prior art, fuse bits were stored outside of main memory.
With reference to FIG. 1, a known micro-controller 11, such as Atmel Corporation's AT89CX051 is connected by a 2-wire bus 13 to a plurality of non-volatile memory devices, such as the serial memories 21 . . . 29. In the protocol described below and in this application, up to 8 serial memories may be connected to bus 13. The number of serial memories could be expanded with certain modifications of the addressing system. A typical serial memory is one of Atmel Corporation's AT24CXX series of devices.
A bidirectional data transfer protocol is utilized by AT24CXX devices of the prior art, allowing a number of compatible devices to share a common 2-wire bus. The bus consists of a serial clock (SCL) line 15 and a serial data (SDA) line 17. The clock is generated by the controller 11, acting as the bus master, and transmitted on line 15 while data is transmitted serially on the data line 17, most significant bit first, synchronized to the clock signal. The protocol supports bidirectional data transfers in 8-bit bytes, although other bit-widths are possible with other memory devices.
The bus master 11 initiates a data transfer by generating a start condition on the bus. This is followed by transmission of a command byte containing the device address of the intended recipient, one of the memory devices 21 . . . 29. The command byte consists of a 4-bit fixed portion and a 3-bit programmable portion that is the device address. The fixed portion must match the value hard-wired into the slave, while the programmable portion allows the master to select between a maximum of eight slaves of similar type on the bus. The memory devices 21 . . . 29, such as AT24CXX serial EEPROMs, receive the command byte with a fixed portion equal to ‘1010’ and a programmable portion matching the address inputs (A0, A1, A2).
The eighth bit in the command byte specifies a write or read operation. After the eighth bit is transmitted, the master 11 releases the data line and generates a ninth clock. If a slave of one of the memory devices 21 . . . 29 has recognized the transmitted device address, it will respond to the ninth clock by generating an acknowledge condition on the data line. A slave which is busy when addressed may not generate an acknowledge. This is true for the AT24CXX when a write operation is in progress.
Following receipt of the slave's address acknowledgment, the master 11 continues with the data transfer. If a write operation has been ordered, the master 11 transmits the remaining data, with the slave acknowledging receipt of each byte. If the master has ordered a read operation, it releases the data line and clocks in data sent by the slave. After each byte is received, the master 11 generates an acknowledge condition on the bus 13. The acknowledge is omitted following receipt of the last byte. The master terminates all operations by generating a stop condition on the bus 13. The master 11 may also abort a data transfer at any time by generating a stop condition.
With reference to FIG. 2, data bus 13 is seen connected to memory device 21 serially communicating with a controller, not shown. The two wires which comprise the data bus 13 are the serial clock line 15 and the serial data line 17, both seen connected to start-stop logic 31, serial control logic 33 and output logic 49. The start-stop logic block 31, in combination with the serial control logic 33, recognizes the device address of memory device 21, thereby initiating the preparation of the ancillary circuits necessary to support a memory read or write operation. These ancillary circuits include a high-voltage pump and timing circuit 37, a data word address counter 35, and data recovery circuit 39. Preparation of the circuits includes supplying chip enable signals, reference or power supply voltage levels, address loading or incrementing signals, etc. The X-decoder 41 and Y-decoder 43, as well as serial multiplexer 47 and output logic 49 and output driver 51, are also prepared for reading or writing a memory word from the memory core 45. The various data bits that enable these ancillary circuits are the fuse bits described in this application. It is seen from FIG. 2 that the enabling and configuring fuse bits are stored outside of the memory core 45, namely in the logic circuits 31 and 33, or alternatively in registers elsewhere in a memory device. It is the storage of fuse bits that the present application addresses.
An object of the invention was to reduce circuitry in a serial memory device, while at the same time not yielding speed or accuracy of the device.